1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device improved to enhance reliability. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background
In an ultra large scale integrated circuit (ULSI), a technique forming an element isolation oxide film isolating an element region from the other element regions is important. As miniaturization progresses, a technique for forming an element isolation oxide film without lowering integration density is required.
A method of forming a conventional element isolation oxide film will be described taking a method of manufacturing a conventional field effect transistor (MOSFET) as an example.
FIGS. 21 to 26 are sectional views schematically showing the steps of manufacturing the conventional MOSFET.
Referring to FIG. 21, an underlay oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1.
Referring to FIG. 22, underlay oxide film 2 and nitride film 3 are patterned so that an opening 4 can be formed on a portion at which an element isolation oxide film is to be formed.
Referring to FIG. 23, impurity ions 6 for forming a channel cut layer 5 are implanted into the surface of semiconductor substrate 1.
Referring to FIG. 24, the surface of semiconductor substrate 1 is oxidized with nitride film 3 used as a mask, thereby forming an element isolation oxide film 7 in the surface of semiconductor substrate 1. Referring to FIGS. 24 and 25, underlay oxide film 2 and nitride film 3 are removed. This method is called an LOCOS (Local Oxidation of Silicon) method.
Referring to FIG. 26, a field effect transistor (MOSFET) 8 is formed in an element region.
Description will now be given of problems of a method of manufacturing a conventional semiconductor device with the LOCOS method.
Referring to FIG. 27, the pattern of underlay oxide film 2 and nitride film 3 is formed on semiconductor substrate 1.
Referring to FIG. 28, with nitride film 3 used as a mask, the surface of semiconductor substrate 1 is thermally oxidized to form element isolation oxide film 7. A region in which element isolation oxide film 7 is formed is called a field region 105, and a region in which the MOSFET element is formed is called an element region 106. A bird's beak 9 extends from field region 105 to element region 106. Channel cut layer 5 formed under element isolation oxide film 7 is for electrical isolation between elements. A parasitic MOSFET exists in field region 105. In order to electrically isolate elements, the threshold voltage of the parasitic MOSFET must be increased so that it will not operate. For this purpose, channel cut layer 5 is provided.
In order to increase integration density, it is necessary to reduce the lateral length of field region 105. In order to reduce field region 105, it is necessary to reduce the lateral length of bird's beak 9. Bird's beak 9 becomes longer as the oxidation temperature is higher, and the thickness of nitride film 3 becomes smaller. Attempts to lower the oxidation temperature or to increase the thickness of nitride film 3 are made in order to shorten the length of bird's beak 9. However, these attempts do not result in extremely short bird's beak 9.
Referring to FIG. 28, when the semiconductor substrate is oxidized at a low temperature with nitride film 3 increased in thickness, an SiO.sub.x layer 10 is formed at a boundary between element isolation oxide film 7 and semiconductor substrate 1. Excessive interstitial silicon (Si.sup.+) which is left unreacted at the time of oxidation reaction exists in SiO.sub.x layer 10, as shown in FIG. 29. If excessive interstitial silicon exists at high density in SiO.sub.x layer 10, stress concentrates in the surface of semiconductor substrate 1, causing lattice defects to be formed. In addition, a number of unsaturated bond hands of silicon atoms (Si--Si bond) in SiO.sub.x layer 10 cause trap. Such lattice defects and unsaturated bond hands of silicon atoms cause leakage current, preventing electrical isolation between elements. Since particularly large stress is applied to an end portion of element isolation oxide film 7, a number of small lattice defects are formed in this portion.
With miniaturization of the MOSFET element, the element isolation width decrease. Therefore, depending on the condition of an applied voltage of an element, electric field of approximately several hundred kV/cm is applied to field region 105. Since leakage current is more likely to occur than the conventional case, the above problems become more serious.
Besides the existence of lattice defects and unsaturated bond hands of silicon described above, a small defect also causes leakage current. The procedure of formation of such a small defect will be described. As a material of the ULSI, a semiconductor substrate of a silicon single crystal formed with a Czochralski pulling up process is used. Since the mechanical strength of the semiconductor substrate becomes stronger as the oxygen concentration in the substrate becomes higher, the silicon single crystal is formed such that oxygen atoms of 10.sup.18 /cm.sup.3 or more are included in the substrate. During the heat treatment for manufacturing the ULSI, however, oxygen which exists in the substrate at a high concentration precipitates, and the precipitated oxygen reacts with silicon to form SiO.sub.2. Since the volume of the precipitates becomes approximately double at this time, silicon atoms are released in the place where the precipitates is generated, resulting in excessive interstitial silicon. The interstitial silicon atoms get together to form stacking faults or small defects such as dislocation.
The above problem also appears in a method of forming an element isolation oxide film using an SWAMI (Side Wall Masked Isolation) structure shown in FIGS. 30 to 35. In the LOCOS isolation method, bird's beak 9 was not made extremely short, and prevented integration. As measures against this, the SWAMI structure is proposed. Description will now be given of a process for forming the SWAMI structure.
Referring to FIG. 30, underlay oxide film 2 is formed on the surface of semiconductor substrate 1. Nitride film 3 is formed on a portion where an element region is to be formed on underlay oxide film 2.
Referring to FIGS. 30 and 31, underlay oxide film 2 is selectively etched with nitride film 3 used as a mask. Then, the surface of semiconductor substrate 1 is anisotropically etched with nitride film 3 used as mask. Then, an oxide film 11, a nitride film 12, and an oxide film 13 are sequentially formed on semiconductor substrate 1 so as to cover nitride film 3.
Referring to FIGS. 31 and 32, oxide film 13 and nitride film 12 are anisotropically etched.
Referring to FIGS. 31 and 32, oxide film 13 is partially etched away. Then, referring to FIGS. 32 and 33, oxide film 11 is partially etched away. When the surface of semiconductor substrate 1 is oxidized, element isolation oxide film 7 as shown in FIG. 33 is formed. Since nitride film 12 is also formed at side walls of nitride film 3, the length of bird's beak 9 is made extremely smaller as compared to that formed with an ordinary LOCOS method. Referring to FIGS. 34 and 35, nitride film 3, nitride film 12, and underlay oxide film 2 are removed, and element region 106 and field region 105 are formed.
The SWAMI structure has an advantage that the length of bird's beak 9 can be suppressed. However, since nitride film 12 formed at the side walls suppresses an end portion of the element isolation oxide film, stress concentrates at the end portion of element isolation oxide film 7, causing lattice defects and small defects to be formed at a boundary between element isolation oxide film 7 and semiconductor substrate 1. The lattice defects and small defects cause leakage current.
FIG. 36 is a sectional view of a semiconductor device having element region 106 and element isolation region 105 formed with a trench isolation method.
Referring to FIG. 36, a first groove 113 and a second groove 115 are formed in the surface of semiconductor substrate 1. An impurity layer 118 and an impurity layer 120 are formed in the inner wall surface of second groove 115. An oxide film 116 is formed so as to cover the sidewall surface of second groove 115. An oxide film 119 is provided at the bottom surface of second groove 115 so as to join oxide film 116. Polysilicon 117 fills second groove 115. An oxide film 114 is provided at the side wall of first groove 113. An oxide film 112 is provided on the surface of semiconductor substrate 1 so as to surround first groove 113. With such a trench isolation method, semiconductor substrate 1 is divided into element isolation region 105 and element region 106. An element such as an MOSFET is formed on element region 106. The trench isolation method has an advantage that the element isolation width can be made small, since there is no bird's beak. However, lattice defects are formed at a boundary between oxide film 116 covering the inner wall surface of second groove 115 and semiconductor substrate 1, causing leakage current.
Description will now be given of how lattice defects cause leakage current.
When a reverse bias is applied to a pn junction, a depletion layer is formed in the vicinity of the junction. In the depletion layer, high electric field is applied depending on the bias condition. The width W of the depletion layer depends on impurity distribution as shown by the expression (1). ##EQU1##
In the expression (1), .epsilon..sub.s is a dielectric constant, .epsilon..sub.o is a dielectric constant in vacuum, q is a unit charge, N.sub.A is an acceptor concentration, N.sub.D is a donor concentration, V.sub.bi is a built-in potential, and V.sub.R is a reverse bias voltage.
Leakage current caused by lattice defects is generated in the Shockley-Read-Hall process (hereinafter referred to as an "SRH process"). The SRH process is based on four phenomena as shown in FIGS. 37A to 37D.
In FIGS. 37A to 37D, reference character 132 denotes an end of a conduction band, reference character 133 denotes an end of a valence band, reference character 134 denotes an electron in the conduction band, reference character 135 denotes the trap center (trap), and reference character 136 denotes a hole in the valence band. The trap center (trap) refers to an unsaturated bond hand of a silicon atom, or the like, in a silicon substrate or an oxide film.
In FIG. 37A, an electron of the conduction band is captured by the trap. In FIG. 37B, the electron captured by the trap is released, and transitions to the conduction band. In FIG. 37C, a hole in the valence band transitions to be captured by the negatively charged trap, so that the trap becomes neutral. In FIG. 37D, the hole captured by the trap is released, and transitions to the valence band. A net recombination velocity U is given by the expression (2). ##EQU2##
In the expression (2), n is an electron concentration, p is a hole concentration, n.sub.i is an intrinsic carrier concentration, .tau..sub.po is a reciprocal number of a product of a trap density and a velocity at which the trap captures a hole, and .tau..sub.no is a reciprocal number of a product of the trap density and a velocity at which the trap captures an electron.
n.sub.o and p.sub.o are given by the expressions (3) and (4), respectively. EQU n.sub.o =n.sub.i exp[(.epsilon..sub.t -.epsilon..sub.i)/k.sub.B T](3) EQU p.sub.o =n.sub.i exp[(.epsilon..sub.i -.epsilon..sub.t)/k.sub.B T](4)
In the expressions (3) and (4), .upsilon..sub.t and .upsilon..sub.i are a trap level and an intrinsic Fermi level, respectively, k.sub.B is a Boltzmann's constant, and T is an absolute temperature.
Current I.sub.gen generated in the depletion layer formed by application of a reverse bias to the pn junction is given by the expression (5). EQU I.sub.gen =q.vertline.U.vertline.WA (5)
In the expression (5), A is a cross sectional area of the pn junction. At the time of application of a reverse bias, diffusion current is generated in an intermediate charge region at both ends of the depletion layer, that is, in a neutral p-type impurity layer and a neutral n-type impurity layer. Diffusion current I.sub.diff,n of an electron in a p region is given by the expression (6). ##EQU3##
Diffusion current I.sub.diff,p of a hole in an n region is given by the expression (7). ##EQU4##
In the expressions (6) and (7), Dn, Dp are diffusion coefficients of an electron and a hole, and L.sub.n, L.sub.p are diffusion lengths of an electron and a hole. Therefore, current I.sub.R at the time of application of a reverse bias is given by the expression (8). ##EQU5##
The expression (8) represents leakage current. Since np&lt;&lt;n.sub.i.sup.2 in the depletion layer, U can be approximated as follows. ##EQU6##
In the expression (9), .sigma..sub.c is a trap sectional area, V.sub.th is a velocity of carriers, and N.sub.t is a density of the trap center. It is found from the expressions (8) and (9) that the greater the density of the trap center and the width of the depletion layer, the greater the leakage current. If a higher electric field is applied to the depletion layer, carriers generated in the depletion layer are accelerated to the electric field, causing impact ionization, and generating new electrons in the conduction band. As a result, leakage current increases. As a method of controlling leakage current caused by the SRH process, it is considered to decrease the trap density in the vicinity of the pn junction, or to increase the concentration of the pn junction to suppress the extension of the depletion layer.
Other than the above, degradation of an LOCOS oxide film formed for element isolation is considered to cause leakage current. More specifically, with miniaturization of the ULSI, the element isolation width becomes smaller, and strong electric field is more likely to be applied to the LOCOS oxide film. Therefore, hydrogen atoms attracted by the electric field drift from a film deposited on the LOCOS oxide film to a boundary surface between the LOCOS oxide film and the substrate, and form trap to reduce the threshold voltage of a parasitic transistor. As a result, leakage current is generated. Therefore, in forming an LOCOS oxide film or a trench oxide film, it is inevitable for enhancement of reliability of the element isolation oxide film to decrease as much as possible the number of hydrogen atoms in the oxide film, and to decrease as much as possible the number of unsaturated bond hands of silicon atoms in the oxide film causing trap.
As described above, in any method where elements are isolated in the LOCOS structure, the SWAMI structure, or the trench structure, lattice defects generated by thermal stress between silicon oxide films caused leakage current, preventing perfect electrical isolation.
Also in the conventional LOCOS structure, a problem was leakage current caused by lattice defects at a small density which exist in the vicinity of the pn junction between the drain impurity layer and the channel cut impurity layer directly under the LOCOS oxide film.
Since the element isolation width of the LOCOS oxide film for element isolation becomes smaller with miniaturization of the ULSI, the electric field applied to the LOCOS oxide film becomes larger. As a result, trap is more likely to be generated by drifting of hydrogen atoms from a film deposited on the LOCOS oxide film to a boundary surface between the LOCOS oxide film and the silicon substrate. The trap decreases the threshold voltage of a parasitic MOSFET, and generates leakage current.